1. Technical Field
The present invention relates to a clock display device, and in particular, to a clock display device that uses an LCD or the like and has a programmable display allocation function.
2. Related Art
LCD panels for visibly displaying various types of information are provided at portable terminals, electronic equipment and the like. Clock display is an example of the state of the display thereof. FIG. 5 shows an example of the structure of a conventional LCD clock display circuit for carrying out clock display on an LCD panel. This LCD clock display circuit is structured such that a CPU (Central Processing Unit) 101, a ROM (Read-Only Memory) 102, and a real-time clock (RTC) circuit 105 and the like transmit and receive predetermined information via a system bus 120.
In the conventional LCD clock display circuit, the real-time clock circuit 105, that is provided at a clock information generating circuit 103, generates clock information, and, at a fixed cycle, generates an interruption with respect to the CPU 101. When the CPU 101 receives an interruption request from the real-time clock circuit 105, the CPU 101 reads-out the clock information from the real-time clock circuit 105, and processes the data in order to display the information on an LCD panel 130. Then, due to the CPU 101 writing the processed data to an LCD display register 108 that structures an LCD control circuit 107, clock display on the LCD panel 130 is carried out.
On the other hand, Japanese Patent Application Laid-Open (JP-A) No. 7-120571 discloses a technique (clock counter and semiconductor integrated circuit device incorporating the clock counter therein) of transferring clock information, that is generated at a clock counter, to a display system driver section by a DMA (Direct Memory Access) section, and carrying out clock display.
When carrying out clock display by the above-described conventional LCD clock display circuit, the CPU 101 always receives an interruption request from the real-time clock circuit 105 at a fixed cycle. Therefore, at the conventional LCD clock display circuit, even in a halt mode, i.e., even when the clock supply to the CPU 101 is stopped and the CPU 101 is in a state in which operation thereof is suspended, there is the need to come out of the halt mode and transition to the usual operation mode by starting the supply of the clock. This means that the halt mode cannot be maintained because of the clock display. As a result, in a conventional LCD clock display circuit, there is the problem that a reduction in the current that is consumed (the electric power that is consumed) at the CPU cannot be devised, and wasteful consumption of electric power occurs.
Further, in the conventional LCD clock display circuit, when clock display is carried out at the LCD panel 130, the data that is transferred to the LCD display register 108 must be processed so as to conform to the LCD panel 130. If the LCD panel 130 is a 7-segment type display device for example, in a case in which the hours, minutes and seconds are managed as the clock information by 4-bit decimal numbers, the clock information within the real-time clock circuit 105 must be data processed in accordance with the conversion table shown in FIG. 6.
FIG. 7 shows an example of the data processing of the clock information. When the one-second register value is 4, only the low-order four bits of the data within the register are valid, and therefore “0100” (a decimal) is processed to “01100110” as the character value for a 7-segment type LCD. Accordingly, carrying out such processing of display data on all of the hour, the minute and the second each time display is carried out causes in the problems of complicating processing at the CPU and increasing the load on the CPU.
Processing of display data such as described above is problematic also in the device disclosed in JP-A No. 7-120571. Namely, this is because, in the device disclosed in JP-A No. 7-120571, transfer of clock information using DMA is carried out and the load on the software is reduced, but at the display system driver section that receives the clock information generated at the clock/calendar function section, there is the need to separately process, for LCD display, this clock information.